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44-Pin Demo Board User’s Guide
EXAMPLE 3-8:
org 0
TIMER0 EXAMPLE
BSF
STATUS,RP0
; Bank 1
MOVLW
b'00000111' ; configure Timer0.
; Processor clock
Sourced from the
MOVWF
CLRF
CLRF
BCF
ForeverLoop:
OPTION_REG
TRISD
Display
STATUS,RP0
; Maximum Prescaler
; Make PortD all output
; Bank 0
BTFSS
GOTO
BCF
INTCON,T0IF ; wait here until Timer0 rolls over
ForeverLoop
INTCON,T0IF ; flag must be cleared in software
INCF
MOVF
MOVWF
GOTO
Display,f
Display,w
PORTD
ForeverLoop
; increment display variable
; send to the LEDs
3.2.10
Lesson 10: Interrupts
New Instructions
RETFIE
SWAPF
Return from Interrupt
Swap nibbles in file register
Interrupt Sources
Most of the peripherals can generate an interrupt, and some of the I/O pins may be
configured to generate an interrupt when they change state.
When a peripheral needs service or an event occurs, it sets its interrupt flag. Each
interrupt flag is ANDed with its enable bit and then these are ORed together to form a
Master Interrupt. This master interrupt is ANDed with the Global Interrupt Enable (GIE).
See the Interrupt Logic Figure in the PIC16F882/883/884/886/887 Data Sheet
(DS41291) for a complete drawing of the interrupt logic. The enable bits allow the PIC
microcontroller to limit the interrupt sources to certain peripherals.
FIGURE 3-9:
Interrupt Flag
Interrupt Enable
INTERRUPT LOGIC SIMPLIFIED
Master Interrupt
Global Interrupt Enable
Other Interrupt Sources
DS41296B-page 28
? 2007 Microchip Technology Inc.
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